A telemetry signal analog source is a specialized device for generating front-end input signals for analog signal processors, telemetry component testing, and delivery testing. The signal source generates various types of signals and inputs them to the product to be tested. When testing, the signal generated by the analog source of the telemetry signal and the signal after passing through the product to be tested are compared to determine whether the function of the product is normal. The board in the design is part of the analog source of the telemetry signal, and is mainly used to test whether the function of the LVDS bus protocol of the product is normal. Due to the special application of the signal to be tested, the board is required to receive high-speed serial data within 200 Mbit·s-1 and can transmit LVDs data of any rate from 10 to 50 Mbit·s-1. Due to the high speed, good compatibility, high reliability and low cost of the PCI bus, it has obvious advantages in various bus technologies for communication with the host. FPGA is rich in resources, fast, and easy to develop, so it is widely used in high-speed data communication. The DDS frequency synthesis technology realizes the frequency modulation phase modulation of the output signal through the control of the frequency control word, the phase control word and the reference clock, and the output signal has the advantages of fast frequency conversion, high frequency resolution and low phase noise. Based on the above characteristics, the PCI9054 is used to realize the PCI bus interface. The FPGA implements data receiving and transmitting control and interface implementation. The DDS chip AD9851 generates any LVDS data transmission clock. Finally, the MFC is used to implement the board's interactive interface and test the board.
1 hardware design
The data receiving system collects, processes and stores the target signal to form a data format that the computer can process, that is, includes a signal input unit, a signal processing unit, and a signal output unit. The data transmission system transmits the target data to the lower computer, and the lower computer performs data format processing, and then transmits the data through the signal output unit according to the data protocol form. In addition to this, the entire system also needs support for related modules such as buffers, clocks, and power supplies. Figure 1 shows the hardware design block diagram of the board.
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1.1 PCI interface design
PCI bus is a strict external device interconnect bus developed by Intel and other companies. It is a local bus widely used in computers. Its signal line includes 32 address data multiplexing lines, arbitration, interface control lines, and bus command words. Sections allow multiplexing lines and system resets, etc. PCI interface design generally adopts two methods: (1) It is realized by CPLD/FPGA. This method can customize functions for its own needs and has great design flexibility. (2) Use common interface chips, such as S5933 from AMCC and PCI9054 from PLX. Due to the complexity of the PCI bus protocol, it is time-consuming and labor-intensive to design the interface by itself, and the PCI interface chip has the characteristics of simple design, powerful function and good reliability, thereby greatly reducing the development workload. In summary, the design uses PCI90 54, C slave mode operation, the local bus terminal input clock 50 MHz, the configuration chip is Mierochip Technology's 93LC56 serial EEPROM.
1.2 LVDS interface design
Low Voltage Differential Signaling (LVDS) uses a very low voltage swing to transmit data at high speeds, enabling point-to-point or point-to-multipoint connections. The Cyclone I series EP1C6Q240 FPGA is used in this paper. It supports high-speed LVDS interface. It uses its I/O LVDS driver to convert the FPGA internal logic signal into a low-voltage differential signal pair, which is transmitted to the opposite differential receiving circuit through the transmission line. In Cyclone I series FPGAs, using the LVDS interface simply calls Alt lvds and customizes it in the MegaWizard of its companion Quartus II software.
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The design of the LVDS interface circuit is shown in Figure 2. The FPGA transmitter sends differential signals through LVDS. A 120 Ω resistor is connected in series on the differential line, and a 170 Ω resistor is connected in parallel to weaken the amplitude of the differential signal. The signal is oscillated; the receiving end of the FPGA is connected to a 100 Ω terminating resistor between the differential lines. The current mainly forms a loop through the terminating resistor, thereby forming a differentially received signal voltage at the input end of the receiver; preventing high-speed signal crosstalk of the LVDS during PCB wiring. And mutual interference, to avoid other signals coupled to the LVDS transmission line, should try to distribute the LVDS signal and other signals on the two signal layers.
1.3 Other interface design
In order to meet the DMA transfer characteristics of the PCI bus, a buffer needs to be added to the hardware. The higher the LVDS rate entered, the larger the buffer capacity required to ensure no data loss. Therefore, the design uses the MT48LC2M32 SDRAM provided by Micron as a buffer. It is a 64 MB fully synchronous SDRAM. In addition, the output LVDS signal is arbitrarily adjustable in the frequency range of 10 to 50 MHz. Therefore, AD9851, a direct digital synthesizer manufactured by AD Company using CMOS technology, has a maximum operating clock of 180 MHz. In addition to the complete high-speed DDS, It also integrates a clock 6 multiplier and a high speed comparator, and its interface control is simple. It can directly input frequency, phase and other control data with an 8-bit parallel port or serial port. In the design, the 30 MHz clock is output through the PLL in the FPGA, the frequency multiplier multiplies the reference clock to 180 MHz, and the control interface uses parallel port transmission.
In addition, the clock module uses an active crystal to provide a 50 MHz clock for the system. The SDRAM clock is synthesized by the internal PLL of the FPGA. The power module uses a simple LDO (Low Dropout Regulator) to provide 3.3V and 1.5V power supply voltage.
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